This skill automates the complex process of planning new features for embedded systems such as nRF52 or STM32. It utilizes specialized agents for discovery, AST-based codebase analysis, and architectural design to ensure new features respect memory constraints, task priorities, and existing data structures. By generating structured planning artifacts—including call graphs, memory budgets, and dependency-aware task lists—it provides a robust roadmap for implementing FreeRTOS tasks, Zigbee clusters, or peripheral drivers with high reliability and technical debt prevention.
Key Features
01Automated memory budget estimation for Flash and RAM
02AST-based call graph and symbol cross-reference analysis
0318 GitHub stars
04Multi-agent orchestration for specialized research and design
05Dependency-aware task decomposition with testable acceptance criteria
06FreeRTOS task interaction and ISR mapping
